exploring the vliw architecture space for network applications

the increasing diversity in packet-processing applications together with the rapid increase in channel bandwidth has brought about greater complexity in communication protocols. also influenced by these factors is the computational load for packet-processing engines, demanding high performance microprocessor designs as an indispensable solution. this paper reports on extensive simulation experiments carried out for exploring the performance of instruction-level parallel very long instruction word (vliw) processors executing packet-processing applications. on the grounds of the experimental results, a design space exploration has been used to derive an efficient application-specific vliw processor architecture based on the vex instruction set architecture. the vex simulator toolset has been used for design space exploration, and a number of networking applications have been chosen to serve in guiding the architectural exploration. the optimization measures achieve up to 60% improvement in performance for the most representative packet-processing applications.